| The radio frequency circuit is the RF circuit, which refers to the radio frequency current, which is the abbreviation of a high-frequency alternating electromagnetic wave. When the alternating current of the circuit changes less than 1000 times per second, it is called low-frequency current, and when it is greater than 1000 times, it is called high-frequency current, and radio frequency refers to high-frequency current.
A radio frequency circuit refers to a circuit in which the electromagnetic wavelength of the processing signal is on the same order of magnitude as the circuit or device size. At this time, due to the relationship between the size of the electronic device and the size of the wire, the circuit needs to be processed with the relevant theory of distribution parameters. This type of circuit can be considered as a radio frequency circuit, and there is no strict requirement for its frequency, such as the AC transmission line for long-distance transmission (50Hz Or 60Hz) Sometimes it is also dealt with by the relevant theory of RF.
Next, FS PCBA takes the mobile phone RF circuit as an example to introduce the principle of the RF circuit in detail.
The structure and working principle of the radio frequency receiving circuit:
When the mobile phone is receiving the signal, the antenna converts the electromagnetic wave sent by the base station into a weak alternating current signal. After filtering and high-frequency amplification, it is sent to the intermediate frequency for demodulation, and the received baseband information (RXI-P, RXI-N, RXQ-P, RXQ-N) is obtained, which is sent to the logic audio circuit for further processing.
Circuit Analysis - Circuit Structure:
The receiving circuit is composed of antenna, antenna switch, filter, high-amplification tube (low noise amplifier), intermediate frequency integrated block (receiving demodulator) and other circuits. Early mobile phones had primary and secondary mixing circuits, the purpose of which was to lower the receiving frequency before demodulation.
The structure and working principle of the transmitting circuit
When transmitting, the transmitting baseband information processed by the logic circuit is modulated into the transmitting intermediate frequency, and the frequency of the transmitting intermediate frequency signal is changed to 890M-915M (GSM) frequency signal by TX-VCO. After being amplified by the power amplifier, it is converted into electromagnetic waves by the antenna and radiated out.
Circuit Analysis - Circuit Structure:
The transmission circuit is composed of transmission modulator, transmission phase detector, transmission voltage-controlled oscillator (TX-VCO), power amplifier (power amplifier), power controller (power control), transmission transformer and other circuits inside the intermediate frequency.
The structure and working principle of the local oscillator circuit (local oscillator circuit, phase-locked loop circuit, frequency synthesis circuit)
The circuit generates four sections of local oscillator frequency signals (GSM-RX, GSM-TX, DCS-RX, DCS-TX) without any information, and sends them to the IF. The baseband information is modulated and transmitted phase-detected.
Circuit Analysis - Circuit Structure: There are four circuit structures in the mobile phone local oscillator circuit:
a) Composed of frequency synthesis integrated block, receiving voltage-controlled oscillator (RX-VCO), 13M reference clock, and preset frequency reference data (SYN-DAT, SYN-CLK, SYN-RST, SIN-EN)
b) Integrate the frequency synthesis integrated block inside the intermediate frequency, combined with an external RX-VCO (multi-purpose for mid-term phones and Nokia phones)
c) Integrate the frequency synthesis integrated block and the receiving voltage-controlled oscillator (RX-VCO), called the local oscillator integrated block (multi-purpose for mid-term and Samsung phones)
d) Integrate the frequency synthesis integrated block and the receiving voltage-controlled oscillator (RX-VCO) inside the intermediate frequency (multi-use for new models and miscellaneous brands).
It is worth noting that no matter what kind of structural mode is adopted, only the generated frequency is different, and its working principle, direction and function of the generated frequency signal are the same.
Application of radio frequency circuit
RF technology is widely used in many fields, such as: TV, radio, mobile phone, radar, automatic identification system, etc. The term RFID (radio frequency identification) refers to the application of radio frequency identification signals to identify objects. RFID applications include:
1. ETC (Electronic Toll Collection)
2. Railway rolling stock identification and tracking
3. Container identification
4. Identification, authentication and tracking of valuables
5. Object management for commercial retail, healthcare, logistics services, etc.
6. Access control management
7. Animal identification and tracking |
| PCB wiring is a key factor in ESD protection, FS Technology believes that a reasonable PCB design can reduce unnecessary costs caused by fault inspection and rework. In PCB design, it is more important to overcome the electromagnetic interference (EMI) electromagnetic field effect generated by the discharge current, because the transient voltage suppression stopper (TVS) diode is used to suppress the direct charge injection caused by the ESD discharge.
This article will provide optimized ESD protection for PCB design criteria.
1. Circuit loop.
When current enters circuit loops by induction, these loops are closed and have variable magnetic flux. The current range is proportional to the area of the ring. Larger loops contain more magnetic flux and therefore have stronger current induction in the circuit. Therefore, the loop area must be reduced. The most common loop consists of power and ground wires.
Multilayer PCB designs employ power and ground planes, where possible. Multilayer circuit boards not only minimize the circuit area between power and ground, but also reduce the high-frequency EMI electromagnetic fields generated by ESD pulses. If multilayer boards were not possible, FS Technology would have to connect the circuits for the power and ground lines into a grid. The grid connection can play the role of power and ground, and the printed lines of each layer should pass through holes and the connection interval in each direction should be within 6 cm. In addition, when wiring, the power and ground printed lines produced by FS Technology are as close as possible, which can also reduce the loop area.
Another way to reduce loop area and induced current is to reduce parallel paths between interconnects. When a signal cable longer than 30 cm must be used, a protective wire can be used. A better approach is to place the ground near the signal lines. The signal line should be within 13mm of the protection line or grounding line. Arrange long signal wires (>30cm) or power wires and their ground wires of each sensitive element in a crossover. Crossovers must be separated from top to bottom or left to right.
2. The length of the circuit connection.
Long signal lines can also be used as antennas for receiving ESD pulse energy. Trying to use short signal lines can reduce the efficiency of antennas receiving ESD electromagnetic fields. In order to reduce the printed line length of the interconnection, FS Technology will try to place the interconnection equipment in the adjacent position.
3. Inject the ground charge.
Direct discharge of ESD to the ground plane can damage sensitive circuits. Use one or more high frequency bypass capacitors between the power and ground of the consumables. Bypass capacitors reduce charge injection and maintain the voltage difference between the power and ground ports. The TVS shunts the induced current, maintaining the potential difference of the TVS clamping voltage. To reduce parasitic inductive effects, TVS and capacitors should be placed as close as possible to the protected IC. |
| 1. The PCB must have a Mark point corresponding to the positioning of the entire board on the diagonal of the long side of the board.
Chips with an IC pin center distance of less than 0.65mm on FS Technology’s circuit boards should have a Mark point corresponding to the chip positioning on the diagonal of the long side of the IC; when there are patches on both sides of the pcb, both sides of the pcb should be Add Mark points based on this article.
2. The edge of the PCB should retain the 5mm process edge (the minimum spacing requirement for the machine to clamp the PCB).
Chips whose center-to-center distance between IC pins is less than 0.65mm should be greater than 13mm from the edge of the board (including the edge of the process); the four corners of the board should be chamfered with a φ5 arc. Judging from the current bending degree of PCB wings, the optimal splicing length is about 200mm (equipment processing size: maximum length is 330mm; maximum width is 250mm), try not to spell in the width direction to prevent bending during production.
3. MARK point functions and categories.
Mark points, also known as fiducials, provide a common measurable point for all steps in the assembly process to ensure that each assembly device can accurately locate the circuit pattern. Therefore, FS Technology believes that the Mark point is crucial for SMT production.
4. MARK point design specification recommended by our department.
1) Shape: It is recommended to mark the Mark point as a diameter: R=1.0mm solid circle;
2) Form a complete MARK point, including marked points (or feature points) and open areas.
3) Position: The Mark point is located at the relative position of the diagonal on the veneer or puzzle, and is separated as much as possible; it is best to distribute it at the longest diagonal position (such as the MARK point position diagram).
4) In order to ensure the installation accuracy requirements of FS Technology, SMT requirements: each PCB must have at least one pair of MARK points for the SMT machine to identify, and there must be a single-board MARK (when assembling).
Panel MARK or combined MARK only play a role of auxiliary positioning.
5) When assembling, the relative positions of the MARK points of each single board must be the same.
The position of the MARK point cannot be moved for any reason, resulting in asymmetrical position of the MARK point of each board;
6) All MARK points on the PCB are only valid: two MARKs appearing in pairs on the same diagonal are valid.
So MARK points must appear in pairs to be used (MARK point location map).
fs tech
7) The distance between the MARK point (edge of the open area) and the edge of the PCB must be ≥5.0mm (minimum spacing requirements for the machine to clamp the PCB)
 Requirements for open areas.
Around the mark point marking, there must be an open area with no other circuit features or markings.
The radius of the circle in the open area is R≥2R, where R is the radius of the MARK point.
When R reaches 3R, the machine recognition effect is better.
9) PBC Materials
Mark point markings can be bare copper, which is protected by a transparent anti-oxidant coating. If solder mask (solder mask) is used, the mark point or its open area should not be covered.
10) PBC Contrast.
A. The best identification performance is achieved when there is a high contrast between the mark point markings and the matrix material of the printed board.
B. The internal background must be the same for all mark points.
MARK classification:
1) Mark points are used for solder paste printing and component placement optical positioning.
According to the function of Mark points on the PCB, it can be divided into panel Mark points, single-board Mark points, local Mark points (also known as device-level Mark points),
2) There should be at least three Mark points on the edge of the FS technology paneling process and the veneer that does not need paneling, distributed in an L shape, and the diagonal Mark points are asymmetrical about the center.
3) If there are mounted components on both sides, then there must be mark points on each side.
4) There should be mark points on the board that needs to be assembled as much as possible. If there is no place to place the mark point, the mark point cannot be placed on the board.
5) For QFP with lead center distance ≤ 0.5mm and BGA equipment with center distance ≤ 0.8mm, the local Mark point should be set near the diagonal of the component center point for accurate positioning.
6) If several SOP devices are relatively close (≤100 mm) to form an array, they can be regarded as a whole, and two local Mark points are designed at their diagonal positions. |
| Recently Spotted MembersNo members found. Be the first. |
Requirements for open areas.